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Chapter 3: Design Rules and Procedures
3–13
Frequency Design Rules
For feedback circuitry (the output of a block fed back into the input of a block), a
registered block must be in the feedback loop. Otherwise, DSP Builder creates an
unresolved combinational loop ( Figure 3–13 ).
Figure 3–13. Feedback Loop
Use the PLL block and assign different sampling periods on registered DSP Builder
blocks to design multirate designs.
Alternatively, use a single clock domain with clock enable and the following design
rules to design multirate designs without the DSP Builder PLL block:
■
■
The fastest sample rate is an integer multiple of the slower sample rates. The Clock
Phase Selection field in the Block Parameters dialog box specifies the values for
the Delay block.
The Clock Phase Selection box accepts a binary pattern string to describe the
clock phase selection. DSP Builder processes each digit or bit of this string
sequentially on every cycle of the fastest clock. When a bit is equal to one, DSP
Builder enables the block; when a bit is equal to zero, DSP Builder disables the
block.
Table 3–2 shows some examples of typical clock phase selections.
Table 3–2. Clock Phase Selection Example
Phase
1
10
0100
Description
The Delay block is always enabled and captures all data passing through the block
(sampled at the rate 1).
The Delay block is enabled every other phase and every other data (sampled at the
rate 1) passes through.
The Delay block is enabled on the 2nd phase out of 4 and only the 2nd data out of 4
(sampled at the rate 1) passes through. The data on phases 1, 3, and 4 does not pass
through the Delay block.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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